Intel Core i7 Nehalem 965 XE 3.2GHz review

СPage 3 - Intel Core i7 Nehalem Architecture (part 2)

Quick Path Interconnect (QPI) instead of FSB

We waved FSB goodbye, so an new protocol for replacing it is in order, a protocol that provides the communication between the processor and the North bridge of the motherboard. So Intel came up with Quick Path Interconnect (QPI). This is the protocol's first appearance and if it caches on there will be changes and improvements, but for the time being this is 20 bit interface with two way data communication at the speed of up to 6.4GT/s (at the lower Core i7 models it is 4.8GT/s, with Extreme it is 6.4GT/s).

Less cache and with different architecture

In Core 2 processors the cache varied between 1MB in the dual-core E1xxx Celeron processors, all the way up to 12MB (2x6MB) in the high quad-core Q9xxx ones. Now the cache as whole is less, but works in a different way too. For starters we have 3 levels of cache. The L1 cache is separate for each core - 32KB for information and 32KB for instructions or in other words 256KB L1 cache as whole. The Core i7 L2 cache unlike the one in Core 2, is not shared - an 256KB for each core of the present Core i7 processors gives them a total of 1MB L2 cache. As for the L3 cache - it is shared between the four cores.

Hyper Threading and few new instructions

Hyper Threading is not a new technology. Intel's first attempt at creating multi-threading was by using HT in Pentium 4 Northwood, that undoubtedly reserved itself an honourable place in history. Later with Pentium EE we saw dual-core processor with HT or the ability to execute 4 parallel threads. Intel orchestrated a comeback for this technology and now, quite recently we saw an single core Atom processor with multi-threading thanks to HT, and for a first time we are witnessing parallel execution of 8 threads with the Core i7.

And to make the picture complete, a few words about the new instructions Core i7 obtained are in order. Now Intel are quite well known for their innovations in multimedia technologies, beginning with MMX a decade ago and continuing with SSE, that is currently in its "version" 4 - in Penryn 45nm we saw SSE4.1, having 47 new instructions for accelerating operations with multimedia and now Nehalem runs SSE4.2 - containing 7 new instructions in the pack.